1. Field of the Invention
The invention relates to IBM PC AT-compatible computer architectures, and more particularly, to enhancements thereof for communicating with I/O peripheral devices.
2. Description of Related Art
The IBM PC AT computer architecture has become an industry standard architecture for personal computers and is typically built around a CPU such as an 80286, 80386SX, 80386DX, or 80486 microprocessor manufactured by Intel Corporation. The CPU is coupled to a local bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-50MHz with today's technology). The local bus includes 16 or 32 data lines, a plurality of address lines, and various control lines.
The typical IBM PC AT-compatible platform also includes DRAM main memory, and in many cases a timer, a real-time clock, and a cache memory, all coupled to the local bus.
The typical IBM PC AT-compatible computer also includes an I/O bus which is separate and distinct from the local bus. The I/O bus, sometimes referred to in these systems as an AT bus, an ISA bus or an EISA bus, is coupled to the local bus via certain interface circuitry. The I/O bus includes 8, 16 or 32 data lines, a plurality of I/O address lines, as well as control lines. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by executing a special I/O instruction. Such an I/O instruction generates memory access signals on the local bus, but also activates an MIO# signal to indicate that this is an access to the I/O address space. The MIO# line is often considered as merely another address line. The interface circuitry recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the I/O bus, and if appropriate, returns results to the CPU over the local bus.
In practice, some I/O addresses may reside physically on the local bus and some memory addresses may reside physically on the I/O bus. The interface circuitry is responsible for recognizing that a memory or I/O address access must be emulated by an access to the other bus, and is responsible for doing such emulation. For example, a ROM (or EPROM) BIOS may be physically on the I/O bus, but actually form part of the local memory address space. During system boot, when the CPU sends out a non-I/O address which is physically within the ROM BIOS, the interface circuitry recognizes such, enables a buffer which couples the address onto the I/O bus, and activates the chip select for the ROM. The interface circuitry then assembles a data word of the size expected by the CPU, from the data returned by the ROM, and couples the word onto the local bus for receipt by the CPU. In many systems, at some point during the ROM-based boot-up procedure, the ROM BIOS is copied into equivalent locations in the DRAM main memory and thereafter accessed directly. The portion of DRAM main memory which receives such portions of the BIOS is sometimes referred to as "shadow RAM."
More specifically, in the standard architecture, the logical main memory address space is divided into a low memory range (0h-9FFFFh), a reserved memory range (A0000h-FFFFFh) and an extended memory range (100000h-FFFFFFh). In a typical system the system ROM BIOS is located logically at addresses F0000h-FFFFFh, and is located physically on the I/O bus. Addresses C0000h-EFFFFh contain ROM BIOS portions for specific add-on cards and are located physically on their respective cards on the I/O bus. Addresses A0000h-BFFFFh contain the video buffer, located physically on a video controller on the I/O bus. Duplicate memory space is typically provided in DRAM on the local bus for addresses C0000h-FFFFFh, and the user of the system can select during a setup procedure, which portions of the ROM BIOS are to be "shadowed" by being copied into the duplicate DRAM space during boot-up. Subsequent accesses to "shadowed" portions of the BIOS are to the DRAM copy, which is typically much faster than accesses to the ROM copy.
In addition to the above elements, a keyboard controller typically is also coupled to the I/O bus, as is a video display controller. A typical IBM PC AT-compatible system may also include a DMA controller which permits peripheral devices on the I/O bus to read or write directly to or from main memory, as well as an interrupt controller for transmitting interrupts from various add-on cards to the CPU. The add-on cards are cards which may be plugged into slot connectors coupled to the I/O bus to increase the capabilities of the system.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "PC/AT Technical Reference Manual", in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990) and Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including the "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). All the above references are incorporated herein by reference.
The local bus includes a plurality of address lines and a plurality of data lines, as well as a number of control lines and power and ground. The exact set of lines which make up the local bus is well known in the industry, and may be determined from various sources, including the references cited above. For present purposes, it is sufficient to identify the following signal lines on the local bus ("#" indicates active low):
______________________________________ CA(23:1) or Address lines. For the 80286 and CA(31:2) 80386SX, 24 bits of address are provided. The high order 23 bits are provided on CA(23:1). For the 80386DX and 80486, 32 bits of address are available. The high order 30 bits are provided on CA(31:2). BHE# & BLE# Byte High Enable and Byte Low or BE#(3:0) Enable, or Byte Enables (3:0). For the 80286 and 80386SX, BLE# can be thought of as equivalent to CA(0) and BHE# = !BLE#. For the 80386DX and 80486, BE#(3:0) carries a 1-of-4 decode of the 2 low order address bits CD(15:0) or Data lines. The 80286 and 80386SX CD(31:0) operate with a 16-bit external data bus, and the 80386DX and 80486 operate with a 32-bit data bus. M/IO# Memory/IO control line. When asserted low by the CPU, indicates that the address on CA is an I/O address as opposed to a main memory address. READY# Acknowledgment to CPU that a current request has been serviced and CPU can start a new cycle. CLK2 or CLK CPU clock signal. W/R# Distinguishes write cycles from read cycles. D/C# Distinguishes data cycles, either memory or I/O, from control cycles which are: interrupt acknowledge, halt, and instruction fetching. LOCK# Indicates that other system bus masters are denied access to the system bus while it is active. ADS# Indicates that a valid bus cycle definition and address (W/R#, D/C#, M/IO#, BE0#, BE1#, BE2#, BE3# (or BHE# and BLE#) and CA) are being driven on the local bus. NA# Requests address pipelining. BS16#(386) Allows direct connection of 16- BS8#(486) bit and 8-bit data buses. HOLD Allows another bus master to request control of the local bus. HLDA Indicates that the CPU has surrendered control of its local bus to another bus master. BUSY# Signals a busy condition from a processor extension. ERROR# Signals an error condition from a processor extension. PEREQ Indicates that the processor extension has data to be transferred by the CPU. INTR A maskable input to CPU that signals the CPU to suspend execution of the current program and execute an interrupt acknowledge function. NMI A non-maskable input that signals the CPU to suspend execution of the current program and execute an interrupt acknowledge function. RESET Suspends any operation in progress and places the CPU in a known reset state. ______________________________________
The various signals on the I/O bus are also well specified and well known in the industry. The Solari book identified above described the lines in detail. For present purposes, only the following signals are important:
______________________________________ SA(19:0) 20 address lines. Sufficient to address 1MB of memory. Only SA(15:0) are used to address the 64k I/O address space, and only SA(9:0) are used to address the basio 1k AT I/O address space. Additional address lines for LA(23:17) addressing a 16MB memory address space on the I/O bus. The LA lines are valid earlier in an I/O bus cycle, but must be latched if needed later in the cycle. The SA lines are not valid as early as the LA lines, but remain valid longer. BALE Bus address latch enable In line. In a CPU initiated I/0 bus cycle, this line indicates when the SA address, AEN and SBHE# lines are valid. In other I/O bus cycles, the platform circuitry drives BALE high for the entire cycle. SBHE# System byte high enable. When SBHE# is active and SA(0) is low, then a 16-bit access will be performed. AEN When active, informs I/0 resources on I/O bus to ignore the address and I/O command signals. Used primarily in DMA cycles where only the I/O resource which has requested and received a DMA acknowledgment signal (DACK#) knows to ignore AEN and respond to the I/O signal lines. Some systems include slot-specific AEN signal lines. SD(15:0) 16 data lines. MEMR#, Read request lines to a memory SMEMR# resource on the I/O bus. SMEMR# is the same as MEMR# except that SMEMR#becomes active only when the read address is below 1MB (i.e., LA(23:20) = 0). MEMW# Write request lines to a memory SMEMW# resource on the I/O bus. SMEMW# becomes active only when the write address is below 1 MB. IOR# Read request line to an I/O resource on the I/O bus. IOW# Write reguest line to an I/O resource on the I/O bus. MEMCS16# Memory chip select 16. Asserted by an addressed memory resource on the I/O bus if the resource can support a 16-bit memory access cycle. IOCS16# I/O chip select 16. Asserted by an addressed I/O resource on the I/O bus if the resource can support a 16-bit I/O access cycle. SRDY# Synchronous Ready line. Also sometimes called OWS# or ENDXFR#. Activated by an addressed I/O resource to indicate that it can support a shorter-than-normal access cycle. IOCHRDY I/O channel ready line. lf this line is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. A deactivated IOCHRDY supersedes an activated SRDY#. Also sometimes called CHRDY. MASTER# After requesting and receiving a DMA-acknowledged (DACK#) signal, an I/O bus add-on card can assert MASTER# to become the bus master. REFRESH# Activated by refresh controller to indicate a refresh cycle. IRQ(15, 14, Interrupt request lines to 12:9, 7:3) interrupt controller for CPU. DRQ(7:5, DMA Request lines from I/O 3:0) resource on I/O bus to platform DMA controller. DACK(7:5, DMA Acknowledge lines. 3:0) TC DMA terminal count signal. Indicates that all data has been transferred. BCLK I/O bus clock signal. 6-8.33 MHz square wave. OSC 14.318 MHz square wave. ______________________________________
Recently, efforts have been made to reduce the size and improve the manufacturability of PC AT-compatible computers. Specifically, efforts have been made to minimize the number of integrated circuit chips required to build such a computer. Several manufacturers have developed "PC AT chipsets", which integrate a large amount of the I/O interface circuitry and other circuitry onto only a few chips. An example of such a chipset is the 386WB PC/AT chipset manufactured by OPTi, Inc., Santa Clara, Calif.
In the original IBM PC AT computer manufactured by IBM Corp., the I/O bus operated with a data rate of 8 MHz (BCLK=8 MHz). This was an appropriate data rate at that time since it was approximately equivalent to the highest data rates which the CPUs of that era could operate with on the local bus. Numerous third party vendors have since developed peripheral devices and controller cards which are intended to be plugged into an AT slot on the I/O bus, and which rely upon the 8 MHz maximum data rate. The AT standard also requires a wait state (i.e. 125 nS) for 16-bit data transfers, and four wait states (500 nS) for 8-bit data transfers. A zero wait state data transfer is also available, but only if the peripheral device signals, by activating the SRDY# control line on the I/O bus, that it can handle such fast data transfers.
In the years since the IBM PC AT was originally introduced, technology has improved dramatically to the point where local buses on typical high-end PC AT-compatible computers can operate on the order of 50 MHz. Despite these advances, however, such computers are still manufactured with an I/O bus operating at around 8 MHz because of the need to maintain compatibility with previously designed peripheral devices. These devices were designed in reliance upon the 8 MHz data rate and AT wait state protocol, and many such devices are not capable of operating faster. Even modern designs for AT bus peripherals often rely on the 8 MHz maximum data rate, even though very little additional effort or cost would be involved to design them to operate faster.
In addition to the large disparity between data transfer rates on the I/O bus as compared to the local bus in modern PC AT-compatible computers, the I/O interface circuitry needs to delay its handling of requests and responses from one bus to the other merely because the clocks are not synchronized. The circuitry therefore must hold a request or response until the appropriate clock edge on the destination bus appears. This can add on the order of 30-200 nS to each I/O bus cycle. Accordingly, it can be seen that any access to a peripheral device on the I/O bus imposes a substantial penalty on the performance of PC AT-compatible computers. This penalty will only become worse as the disparity between the local bus and I/O bus data rates continues to increase.
FIG. 1 depicts the important elements of a prior art PC AT-compatible computer architecture 10 which addressed the problem of the I/O bus access penalty with respect to one particularly speed-sensitive peripheral device, namely, a VGA video graphics controller 12. This particular computer system used an ET4000 VGA controller chip, manufactured by Tseng Labs, Newtown, Pa. The ET4000 is described in a data book entitled "ET4000 Graphics Controller High Performance Video Technology", published by Tseng Labs (1990), incorporated herein by reference. The VGA controller 12 shown in FIG. 1 includes this chip, the video memory, a DAC, and all associated circuitry. Although originally intended to be used in a standard configuration as a peripheral device on the I/O bus, the VGA controller 12 is nevertheless capable of operating at the high speeds of the local bus.
A VGA controller in the PC AT-compatible architecture is addressable in two address ranges: I/O ports are accessible at addresses 3B0-3DE in the I/O address space, and the video memory itself is accessible at addresses A0000-BFFFF in the main memory address space. In the original PC AT configuration, the VGA controller was located on the I/O bus and accesses to the I/O ports of the VGA controller occurred in the normal way for peripheral devices. That is, as mentioned above, the CPU issued an I/O read or write command and the I/O interface circuitry recognized it and generated the appropriate signals on the I/O bus in order to read or write from the addressed I/O port on the VGA controller. In order to access the video memory directly, the CPU issued an ordinary read or write cycle on the local bus as if the video memory was physically attached to the local bus. The I/O interface circuitry decoded the address to determine that it was within the address range of video memory, and then generated the appropriate signals on the I/O bus to execute the read or write cycle. When the cycle completed, any data returned by the VGA controller on the I/O bus was transmitted to the local bus. The READY# signal, which would have been asserted to the CPU almost immediately if the video memory was physically on the local bus, is withheld until the I/O cycle is complete.
In the architecture 10 shown in FIG. 1, accesses to the I/O ports of the VGA controller 12 continue to occur via the I/O bus. That is, the VGA controller 12 responds to the control signals on the I/O bus, receives its addressing from the I/O bus, and transfers data via the I/O bus. Similarly, master accesses to or from either port of the VGA controller, as well as DMA data transfers to or from video memory, also continue to occur via the I/O bus. Direct accesses by the CPU to or from video memory, however, occur directly from the local bus.
Referring to FIG. 1, the architecture 10 includes a CPU 20, which may be an Intel 80386SX microprocessor. Importantly, the CPU 10 has only a 16-bit external data bus and a 24-bit address bus. The CPU 20 is coupled to a local bus 22, together with a main memory array 24. The local bus 22 includes, among other things, 16 data lines CD(15:0), address lines CA(23:1) and BHE# and BLE#. For convenience, when referring to multiple CPU address lines herein, the BLE# line is sometimes referred to by its shorthand equivalent, CA(0).
The architecture 10 also includes an I/O bus 30 which includes, among other things, 16 data lines SD(15:0), address lines SA(19:0), and various control lines. Various peripheral devices illustrated as 32 and 34 in FIG. 1 are attached to the I/O bus 30. Such devices may include, for example, a local area network (LAN) card, an IDE disk drive controller, a modem, and so on.
The architecture 10 also includes an I/O interface chipset 40 which implements the I/O interface circuitry referred to above. On the local bus side, it is bi-directionally connected to the address lines CA(23:1), BHE# and BLE#, as well as the data lines CD(15:0). On the I/O bus side, the I/O interface chipset 40 is bi-directionally connected to the address lines SA(19:0) and data lines SD(15:0). The I/O interface chipset 40 includes an Appian System 90/SX chipset, manufactured by Appian Technology, Sunnyvale, Calif. The chipset 40 also includes an MCS1# input which can be activated by external circuitry to inhibit the performance of an I/O bus cycle in response to a local bus command which would otherwise be interpreted by the chipset 40 as requiring such an I/O bus cycle. It is believed that the MCS1# input was originally intended to be activated by a coprocessor which was present on the local bus instead of the I/O bus.
The VGA controller 12 includes, among other things, a partially multiplexed address/data port. On this port, pins DB(15:0) carry 16 data bits multiplexed with the low order 16 bits of an address, and pins A(19:16) carry four higher order address bits. These pins are connected to a dedicated VGA bus 44, different from both the local bus 22 and the I/O bus 30. As described in the above-mentioned Tseng Labs databook, the VGA controller 12 further includes the following signal lines for connecting to the remainder of the system:
______________________________________ CDMW# Input Memory Write signal for writing data to display memory. Typically connected to I/O bus MEMW# line. ADMR# Input Memory Read signal for reading data from display memory or BIOS ROM. Typically connected to I/O bus MEMR# line. MIOW# Input I/O Write signal for writing to VGA control registers. Typically connected to I/O bus IOW# line. CIOR# Input I/O Read signal for reading from VGA control registers. Typically connected to I/O bus IOR# line. WAIT# Output Memory or I/O read/write access should be stretched until this signal deactivates. Typically used to generate I/O bus READY line (i.e., IOCHRDY) ADRE# Output Enables low order 16 address signals onto DB(15:0). Typically, controls buffers which enable the I/O bus address onto DB(15:0), but used differently in the FIG. 1 architecture as hereinafter described. RDMH# Output Enables upper 8-bits of external bi-directional buffer coupling data lines with DB(15:8). Typically controls a buffer which enables coupling of DB(15:8) with the I/O bus data lines SD(15:8), but used differently in the FIG. 1 architecture as hereinafter described. RDML# Output Enables low order 8-bits of external bi-directional buffer coupling data lines with DB(7:0). Typically controls a buffer ooupling DB(7:0) with the I/O bus data lines SD(7:0) but used differently in the FIG. architecture as hereinafter described. DIR Output Signal for controlling the direction of bi-directional buffers coupling DB(15:0) with a data bus. 1 indicates a memory or I/O read from the VGA controller 12; 0 indicates a memory or I/O write to the VGA controller 12. CS16# Output ldentifies the VGA controller 12 as supporting 16-bit memory accesses. Typically connected to I/O bus MEMCS16# line. IO16# Output Identifies the VGA controller 12 as supporting 16-bit I/O accesses. Typically connected to I/O bus IOCS16# line. AEN# Input I/O address valid input Typically connected to I/O bus AEN# line. SBHE# Input Together with SA(0), indicates whether 8- or 16-bit access is intended. Typically connected to receive I/O bus SBHE# line, but connected differently in the architecture of FIG. 1. SFDB# Output 16-bit memory access enable. Same as CS16# but generated earlier. Not used in typical PC-AT compatible computer; used in FIG. 1 architecture to generate an early CS16# type signal which is used for video memory accesses during DMA and master cycles. ROME# Output Enable signal for external video BIOS ROM. ______________________________________
Octal 3-state buffers 50, 52 and 54 couple address lines from the local bus 22 onto the VGA bus 44. In particular, when enabled, buffer 50 couples local bus address lines CA(19:16) onto VGA bus lines A(19:16), buffer 52 couples local bus address lines CA(15:8) onto VGA bus lines DB(15:8), and buffer 54 couples local bus address lines CA(7:0) onto VGA bus lines DB(7:0).
Bi-directional buffers 56 and 58 can further couple data bi-directionally between the data lines of the local bus 22 and the corresponding lines of VGA bus 44. In particular, the local bus side of bi-directional buffer 56 is connected to local bus data lines CD(15:8), and the local bus side of buffer 58 is connected to local bus data lines CD(7:0). The VGA bus side of bi-directional buffer 56 is connected to VGA bus lines DB(15:8), and the VGA bus side of bi-directional buffer 58 is connected to VGA bus lines DB(7:0).
Additional octal buffers 60, 62 and 64 are provided to couple address lines from the I/O bus 30 onto the VGA bus 44. In particular, buffer 60, when activated, couples I/O bus address lines SA(19:16) onto VGA bus lines A(19:16), buffer 62 couples I/O bus address lines SA(15:8) onto VGA bus lines DB(15:8), and buffer 64 couples I/O bus address lines SA(7:0) onto VGA bus lines DB(7:0). Two additional bi-directional octal buffers 66 and 68 are provided to couple data signals bi-directionally between the VGA bus 44 and the I/O bus 30. In particular, the I/O bus side of bi-directional buffer 66 is coupled to I/O bus data lines SD(15:8), and the I/O bus side of bi-directional buffer 68 is connected to I/O bus data lines SD(7:0). The VGA bus side of bi-directional buffer 66 is connected to VGA bus lines DB(15:8), and the VGA bus side of bi-directional buffer 68 is connected to VGA bus lines DB(7:0).
In a standard system, in which all addresses and data for VGA controller 12 are communicated via the I/O bus 30, buffers 50, 52, 54, 56, 58 and 60 are unnecessary and the Output Enables (OE#) for buffers 62, 64, 66 and 68 are driven by the VGA-generated ADRE#, ADRE#, RDMH# and RDML# signals respectively. In the architecture of FIG. 1, these output enables are driven instead by newly defined signals BADRE#, BADRE#, BRDMH# and BRDML# respectively. The output enables (OE#) for buffers 50, 52, 54, 56, 58 and 60 are connected to receive respective newly defined signals LOCAL#, LADRE#, LADRE#, LRDMH#, LRDML# and BUS#. The directional inputs to bi-directional buffers 56, 58, 66 and 68 are all connected to receive the DIR signal generated by the VGA controller 12, as would the equivalent of bi-directional buffers 66 and 68 in a standard architecture.
The OE# signals identified above for the above buffers are all generated by a group of three programmable logic devices and some additional random logic devices in response to the control signals generated by the VGA controller 12, and in response to various signals on the local and I/O buses 22 and 30. The MCS1 signal provided to I/O interface chipset 40 is also generated by such devices. A fourth PLD generates CS16#, substituting for that normally generated by VGA controller 12. All of these signals derive at least in part from a decode of the address lines on the local bus 22 which indicates whenever a local bus access is being performed to or from any address in the video memory address range A0000-BFFFF, and from a decode of I/O bus addresses to the VGA I/O port addresses.
In operation, buffers 60, 62, 64, 50, 52 and 54 are generally enabled to thereby place any address supplied by CPU 20 onto the VGA bus 44. Memory addresses to the video memory range A0000-BFFFF are supplied through buffers 50, 52 and 54 directly from the local bus 22, and all other memory and I/O addresses are supplied through buffers 60, 62 and 64 from the I/O bus 30. Addresses which do not appear on I/O bus 30, and which are not within the video memory address range, are not provided to the VGA bus 44. If an I/O bus cycle occurs which seeks to access any of the I/O ports on VGA controller 12, VGA controller 12 recognizes the I/O address on SA and, through the PLDs and other logic, controls the BADRE#, BRDMH#, BRDML# and DIR signals to respond as required to the I/O bus cycle. The VGA controller 12 is, during this time, essentially disconnected from the local bus 22. Master bus cycles and any DMA cycles which access the VGA I/O ports also occur in this manner. Similarly, if a local bus access occurs to an address outside the video memory address range, the VGA controller 12 remains essentially disconnected from the local bus 22.
If a local bus access occurs to or from an address which is within the video memory address range A0000-BFFFF, the PLDs and associated logic activate the MCS1# input to the I/O interface chipset 40. The chipset 40, which would otherwise have decoded the address, withheld the CPU's READY# signal, and initiated an access to the video memory on the I/O bus 30, is thereby inhibited from doing so. Instead, the OE# signals for the buffers shown in FIG. 1 are controlled to essentially couple the VGA bus 40 to the local bus 22 and to disconnect it from the I/O bus 30. This logic circuitry, in addition to the VGA controller 12, controls the operation of the buffers 50, 52, 54, 56 and 58 such that the VGA controller 12 responds to the video memory access as if it were physically present on the local bus 22. When the access is complete, one of the PLDs generates an MRDY1# signal to the chipset 40. The chipset 40 activates the READY# line to the CPU 20, and the VGA controller 12 returns to listening on the I/O bus 30.
If an access occurs to or from an address which is within the video BIOS address range, typically C0000h-C8000h, the chipset 40 recognizes this and may initiate a standard AT cycle on the I/O bus 30 for accessing the video BIOS ROM. In a standard architecture, where the VGA controller is physically on the I/O bus, the VGA controller decodes the address on the I/O bus itself in order to generate a ROME# ROM enable signal for the video BIOS ROM. This procedure continues to be used in the architecture of FIG. 1 since, as explained above, the video ROM BIOS addresses which appear on I/O bus 30 will be passed to the VGA controller 12 via buffers 60, 62 and 64.
The FIG. 1 architecture operates, as mentioned above, only with an 80386SX (or lesser) CPU, which has only a 24-bit address bus and 16-bit data bus. The technique incurs a problem when an attempt is made to extend the concept for use with a CPU and local bus which has 32 data lines instead of 16. This is the trend in the personal computer market today, with the advent of such 32-bit external data bus microprocessors as the Intel 80386DX and 80486. These microprocessors also have a 32-bit address bus. The natural extension of the FIG. 1 technique would therefore require adding two more bi-directional buffers similar to 56 and 58 to accommodate the additional data lines and one additional uni-directional buffer similar to 50, 52 or 54 to accommodate the additional address lines. Counting these buffers, the natural extension of the FIG. architecture for a 32-bit external data bus microprocessor therefore requires a total of 13 buffer chips. In addition, further programmable logic and other random logic control circuitry may also be required. Such a large number of chips in an industry moving toward reducing the number of chips required to implement a computer, may in effect prohibit the use of the FIG. 1 technique on newer computers.